PERFTRIGGER1=Val_0x0, PERFTRIGGER2=Val_0x0
Performance Counter Control Register
| PERFTRIGGER1 | Select the internal event that will increment GPU2D_PERFCOUNT1 register. 0 (Val_0x0): Disable performance counter (D2PC_NONE) 1 (Val_0x1): GPU2D active cycles (D2PC_DAVECYCLES) 2 (Val_0x2): Framebuffer read access (D2PC_FBREADS) 3 (Val_0x3): Framebuffer write access (D2PC_FBWRITES) 4 (Val_0x4): Texture read access (D2PC_TXREADS) 5 (Val_0x5): Invisible pixels (enumerated but selected with alpha 0%) (D2PC_INVPIXELS) 6 (Val_0x6): Invisible pixels while internal fifo is empty (lost cycles) (D2PC_INVPIXELS_MISS) 7 (Val_0x7): Display list reader active cycles (D2PC_DLRCYCLES) 8 (Val_0x8): Framebuffer read hits (D2PC_FBREADHITS) 9 (Val_0x9): Framebuffer read misses (D2PC_FBREADMISSES) 10 (Val_0xA): Framebuffer write hits (D2PC_FBWRITEMISSES) 11 (Val_0xB): Framebuffer write misses (D2PC_FBWRITEMISSES) 12 (Val_0xC): Texture read hits (D2PC_TEXREADHITS) 13 (Val_0xD): Texture read misses (D2PC_TEXREADMISSES) 20 (Val_0x14): RLE rewind count (D2PC_RLEREWIND) 31 (Val_0x1F): Every clock cycle (D2PC_CLKCYCLES) |
| PERFTRIGGER2 | Select the internal event that will increment GPU2D_PERFCOUNT2 register. 0 (Val_0x0): Disable performance counter (D2PC_NONE) 1 (Val_0x1): GPU2D active cycles (D2PC_DAVECYCLES) 2 (Val_0x2): Framebuffer read access (D2PC_FBREADS) 3 (Val_0x3): Framebuffer write access (D2PC_FBWRITES) 4 (Val_0x4): Texture read access (D2PC_TXREADS) 5 (Val_0x5): Invisible pixels (enumerated but selected with alpha 0%) (D2PC_INVPIXELS) 6 (Val_0x6): Invisible pixels while internal fifo is empty (lost cycles) (D2PC_INVPIXELS_MISS) 7 (Val_0x7): Display list reader active cycles (D2PC_DLRCYCLES) 8 (Val_0x8): Framebuffer read hits (D2PC_FBREADHITS) 9 (Val_0x9): Framebuffer read misses (D2PC_FBREADMISSES) 10 (Val_0xA): Framebuffer write hits (D2PC_FBWRITEMISSES) 11 (Val_0xB): Framebuffer write misses (D2PC_FBWRITEMISSES) 12 (Val_0xC): Texture read hits (D2PC_TEXREADHITS) 13 (Val_0xD): Texture read misses (D2PC_TEXREADMISSES) 20 (Val_0x14): RLE rewind count (D2PC_RLEREWIND) 31 (Val_0x1F): Every clock cycle (D2PC_CLKCYCLES) |